Analog Electronics MCQs 2026

57 questions with detailed answers · 20 from past papers · 6 quiz batches available

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Page 1 of 1 Questions 110 of 57
  1. Q1 Past Paper · PPSC/FPSC/NTS easy

    A semiconductor diode conducts heavily when

    1. A reverse biased above breakdown always without limit
    2. B unbiased at thermal equilibrium only for heavy conduction
    3. C forward biased beyond knee voltage
    4. D connected in parallel with reverse diode only
    💡 Explanation:

    Forward bias reduces barrier; current rises sharply after knee.

  2. Q2 easy

    Reverse saturation current in an ideal silicon diode at room temperature is

    1. A equal to forward current always
    2. B very small (nanoampere range)
    3. C in the ampere range typically
    4. D proportional to forward voltage squared only
    💡 Explanation:

    Minority carrier diffusion causes tiny reverse current.

  3. Q3 Past Paper · PPSC/FPSC/NTS easy

    Zener diode is primarily used for

    1. A rectification in forward region only
    2. B oscillation without feedback
    3. C current amplification like a BJT
    4. D voltage regulation in reverse breakdown region
    💡 Explanation:

    Zener maintains nearly constant voltage in breakdown.

  4. Q4 medium

    Peak inverse voltage (PIV) rating of a rectifier diode is

    1. A maximum forward current only
    2. B power dissipation at room temperature only
    3. C junction capacitance at zero bias
    4. D maximum reverse voltage the diode can withstand without breakdown
    💡 Explanation:

    PIV defines safe reverse blocking capability.

  5. Q5 easy

    Half-wave rectifier output contains

    1. A pure DC without any ripple
    2. B only one polarity of the input AC waveform
    3. C both polarities equally
    4. D only high-frequency harmonics without fundamental
    💡 Explanation:

    One diode passes alternate half-cycles only.

  6. Q6 Past Paper · PPSC/FPSC/NTS easy

    Full-wave bridge rectifier requires

    1. A two diodes and center tap always
    2. B four diodes and no center-tapped transformer
    3. C one diode only
    4. D six diodes in star connection
    💡 Explanation:

    Bridge uses four diodes to rectify both half-cycles.

  7. Q7 medium

    Ripple factor of a rectifier output indicates

    1. A only DC average without AC content
    2. B reverse breakdown voltage margin
    3. C transistor beta value
    4. D amount of AC component relative to DC component
    💡 Explanation:

    Lower ripple factor means smoother DC output.

  8. Q8 easy

    LED emits light when

    1. A reverse breakdown occurs without recombination
    2. B electrons and holes recombine at the PN junction
    3. C only thermal heating without injection
    4. D gate voltage controls channel only like MOSFET
    💡 Explanation:

    Radiative recombination in direct-bandgap material produces photons.

  9. Q9 Past Paper · PPSC/FPSC/NTS medium

    Schottky diode has lower forward voltage drop than PN junction diode because

    1. A it uses only indirect bandgap silicon always
    2. B it has no depletion region ever
    3. C metal-semiconductor junction has smaller barrier height
    4. D it operates only in Zener breakdown
    💡 Explanation:

    Schottky barrier diodes switch faster with ~0.2–0.4 V drop.

  10. Q10 medium

    Diode dynamic resistance rd is defined as

    1. A slope of V-I curve at the operating point (dv/di)
    2. B reverse saturation current only
    3. C maximum forward current rating
    4. D thermal voltage times beta
    💡 Explanation:

    Small-signal resistance is inverse slope of static characteristic.

  11. Q11 hard

    Avalanche breakdown in a diode occurs when

    1. A forward bias exceeds knee slightly only
    2. B gate oxide ruptures in MOSFET
    3. C only tunneling without multiplication
    4. D minority carriers accelerate and create impact ionization
    💡 Explanation:

    Carrier multiplication in high reverse field causes avalanche.

  12. Q12 Past Paper · PPSC/FPSC/NTS hard

    Tunnel (Zener) breakdown dominates in heavily doped junctions at

    1. A very high reverse voltage only above 100 V always
    2. B forward conduction region only
    3. C lower reverse voltages (typically below about 5 V in silicon)
    4. D only in germanium without silicon
    💡 Explanation:

    Thin depletion layer enables quantum tunneling at low Vz.

  13. Q13 medium

    Varactor diode capacitance varies with

    1. A reverse bias voltage
    2. B forward current only without voltage dependence
    3. C temperature only without bias
    4. D gate threshold in MOSFET sense
    💡 Explanation:

    Depletion width changes with reverse bias modulating capacitance.

  14. Q14 Past Paper · PPSC/FPSC/NTS medium

    Rectifier diode selection must consider

    1. A only LED color wavelength
    2. B forward current rating, PIV and switching speed for the application
    3. C only op-amp slew rate
    4. D only flip-flop clock frequency without power
    💡 Explanation:

    Thermal, voltage and speed ratings ensure reliable rectification.

  15. Q15 easy

    In a common-emitter BJT amplifier, base current controls

    1. A drain current without gate voltage
    2. B only emitter reverse leakage
    3. C large collector current via current gain β
    4. D op-amp offset voltage directly
    💡 Explanation:

    Small IB change modulates IC ≈ βIB in active region.

  16. Q16 medium

    BJT operates in saturation when

    1. A collector-base junction is reverse biased only
    2. B emitter is open circuit
    3. C gate voltage is below threshold
    4. D both junctions are forward biased and VCE is small
    💡 Explanation:

    Saturation: VBE and VBC forward; device acts like closed switch.

  17. Q17 Past Paper · PPSC/FPSC/NTS medium

    Common-collector (emitter follower) configuration has

    1. A low input and high output impedance
    2. B high input impedance and low output impedance
    3. C voltage gain much greater than 100 typically
    4. D inverted output relative to input always
    💡 Explanation:

    Emitter follower provides unity voltage gain with buffering.

  18. Q18 hard

    Audio power amplifier heat sink sizing depends on

    1. A only voltage gain in dB
    2. B only input bias current in pA
    3. C only LED forward voltage
    4. D power dissipation and thermal resistance to ambient
    💡 Explanation:

    Junction temperature must stay below safe limit under load.

  19. Q19 medium

    Emitter degeneration resistor without bypass

    1. A maximizes AC gain unconditionally
    2. B prevents any collector current flow
    3. C stabilizes bias and reduces gain but improves linearity
    4. D replaces the need for coupling capacitor
    💡 Explanation:

    Negative feedback via RE reduces gain variation with temperature.

  20. Q20 Past Paper · PPSC/FPSC/NTS medium

    Op-amp input offset voltage causes

    1. A small DC output error even with zero input signal
    2. B infinite bandwidth always
    3. C oscillation without any feedback
    4. D input impedance to become zero
    💡 Explanation:

    Mismatch in input transistors produces input-referred offset.

  21. Q21 easy

    Non-inverting amplifier closed-loop gain is

    1. A 1 + Rf/R1
    2. B −Rf/R1 only
    3. C Rf/R1 without unity term
    4. D zero always with feedback
    💡 Explanation:

    Positive input amplified by resistive feedback network.

  22. Q22 easy

    Inverting amplifier closed-loop gain is

    1. A 1 + Rf/Rin without sign inversion
    2. B Rf × Rin product only
    3. C independent of feedback resistors
    4. D −Rf/Rin
    💡 Explanation:

    Feedback sets gain to ratio of feedback to input resistors.

  23. Q23 Past Paper · PPSC/FPSC/NTS easy

    Virtual short between inputs of op-amp in negative feedback means

    1. A both inputs are physically shorted externally
    2. B inputs carry equal large current always
    3. C voltage difference between inputs is approximately zero
    4. D output is always saturated
    💡 Explanation:

    High gain forces differential input voltage ≈ 0 in linear region.

  24. Q24 easy

    Ideal operational amplifier has

    1. A zero gain and zero input impedance
    2. B infinite open-loop gain, infinite input impedance and zero output impedance
    3. C finite gain of unity only always
    4. D output impedance equal to 50 Ω always
    💡 Explanation:

    Ideal op-amp assumptions simplify analysis.

  25. Q25 hard

    Safe operating area (SOA) of a transistor specifies

    1. A only maximum power at DC only without pulse duty
    2. B permissible combinations of voltage and current without damage
    3. C only beta at one current point
    4. D only op-amp bandwidth
    💡 Explanation:

    SOA curves include thermal and second-breakdown limits.

  26. Q26 Past Paper · PPSC/FPSC/NTS medium

    FET is preferred in high-input-impedance amplifier front ends because

    1. A gate draws negligible DC current
    2. B collector draws maximum base current
    3. C emitter is always forward biased heavily
    4. D drain current equals gate current always
    💡 Explanation:

    Ultra-low gate leakage suits sensor interfaces.

  27. Q27 medium

    Darlington pair provides

    1. A unity voltage gain only without current gain
    2. B negative input impedance always
    3. C oscillation without feedback guaranteed
    4. D very high current gain with two cascaded transistors
    💡 Explanation:

    Overall β ≈ β1 × β2 for composite device.

  28. Q28 hard

    Channel length modulation in MOSFET is analogous to

    1. A Early effect in BJT
    2. B Zener breakdown in diodes only
    3. C hysteresis in Schmitt trigger only
    4. D sampling aliasing only
    💡 Explanation:

    Short-channel effect raises ID with VDS similar to Early effect.

  29. Q29 Past Paper · PPSC/FPSC/NTS medium

    MOSFET switching speed is generally faster than BJT because

    1. A higher beta always
    2. B larger thermal mass always
    3. C majority carrier transport avoids stored minority charge
    4. D always requires higher supply voltage
    💡 Explanation:

    No minority carrier storage delays turn-off.

  30. Q30 hard

    BJT current gain β decreases at high collector current due to

    1. A only decrease in supply voltage
    2. B only increase in gate threshold
    3. C high-level injection and base spreading resistance effects
    4. D only diode reverse leakage
    💡 Explanation:

    Physical limits and recombination reduce effective β at high IC.

  31. Q31 medium

    Transconductance gm of a FET relates

    1. A small-signal drain current change to gate-source voltage change
    2. B collector current to base current only
    3. C diode forward voltage to current only
    4. D output voltage to supply voltage only
    💡 Explanation:

    gm = ∂ID/∂VGS at the Q-point.

  32. Q32 Past Paper · PPSC/FPSC/NTS medium

    JFET gate input impedance is

    1. A very high because gate junction is reverse biased
    2. B very low like forward-biased diode
    3. C equal to 50 Ω always
    4. D determined by collector load resistor only
    💡 Explanation:

    Reverse-biased gate junction minimizes gate current.

  33. Q33 hard

    Depletion-mode MOSFET differs from enhancement mode in that it

    1. A never conducts without positive VGS always
    2. B has no channel at manufacture
    3. C uses only PNP structure
    4. D conducts with VGS = 0 and requires negative VGS to turn off (n-channel)
    💡 Explanation:

    Depletion devices have built-in channel doping.

  34. Q34 Past Paper · PPSC/FPSC/NTS easy

    Enhancement-mode n-channel MOSFET conducts when

    1. A VGS exceeds threshold voltage positively
    2. B VGS is zero without channel ever
    3. C VDS alone creates channel without gate
    4. D gate is left floating for heavy conduction
    💡 Explanation:

    Positive VGS above Vth induces inversion layer.

  35. Q35 hard

    Early effect in a BJT causes

    1. A gate threshold to decrease only in MOSFET
    2. B collector current to increase slightly with collector-emitter voltage
    3. C diode PIV to double
    4. D inductor core saturation
    💡 Explanation:

    Base-width modulation raises IC with increasing VCE.

  36. Q36 easy

    MOSFET is a

    1. A voltage-controlled device via gate-source voltage
    2. B current-controlled device like BJT base
    3. C majority carrier device only in depletion mode always without exception
    4. D bipolar device with two PN junctions
    💡 Explanation:

    Gate field controls channel conductivity.

  37. Q37 easy

    Coupling capacitor between amplifier stages blocks

    1. A AC signal entirely without DC block
    2. B only high frequencies above 1 MHz always
    3. C feedback path unconditionally
    4. D DC bias while passing AC signal
    💡 Explanation:

    Capacitor passes AC but prevents DC level shift propagation.

  38. Q38 medium

    Class AB amplifier improves on Class B by

    1. A eliminating all feedback
    2. B providing small bias so both devices conduct near crossover
    3. C using only single transistor
    4. D operating only in cutoff always
    💡 Explanation:

    Slight overlap reduces crossover distortion.

  39. Q39 Past Paper · PPSC/FPSC/NTS medium

    Class B push-pull amplifier each transistor conducts for

    1. A full 360° each simultaneously
    2. B approximately 180° of the cycle
    3. C 90° only without crossover region
    4. D 0° so no output ever
    💡 Explanation:

    Each device handles one half-cycle; crossover distortion possible.

  40. Q40 easy

    Class A amplifier conducts

    1. A only 180° of cycle
    2. B less than 90° only
    3. C only during negative half-cycle
    4. D for the full 360° of the input cycle
    💡 Explanation:

    Quiescent current flows continuously; conduction angle 360°.

  41. Q41 easy

    Power amplifier is designed to deliver

    1. A only microvolt signals to high-impedance probes
    2. B logic levels to CMOS gates only
    3. C significant power to the load efficiently
    4. D DC offset calibration only
    💡 Explanation:

    Output stage handles large voltage-current product to load.

  42. Q42 Past Paper · PPSC/FPSC/NTS easy

    Voltage amplifier ideally increases

    1. A current without voltage change
    2. B power factor of mains only
    3. C signal voltage with minimal loading of source
    4. D frequency of carrier without gain
    💡 Explanation:

    Voltage gain Av = Vout/Vin in small-signal models.

  43. Q43 hard

    Rail-to-rail op-amp output stage allows

    1. A output fixed at mid-supply only
    2. B input only on positive rail without negative
    3. C operation without power supplies
    4. D output swing close to both supply rails
    💡 Explanation:

    Extended output range maximizes dynamic range on low supplies.

  44. Q44 medium

    Schmitt trigger using op-amp provides

    1. A pure integration without thresholds
    2. B zero output swing always
    3. C infinite CMRR without resistors
    4. D hysteresis to avoid chatter on noisy input signals
    💡 Explanation:

    Positive feedback creates upper and lower threshold levels.

  45. Q45 Past Paper · PPSC/FPSC/NTS hard

    Gain-bandwidth product of an op-amp is approximately constant for

    1. A all frequencies without rolloff
    2. B single-pole dominant response in closed-loop designs
    3. C DC offset only
    4. D comparator hysteresis only
    💡 Explanation:

    GBW ≈ AOL × BW; closed-loop bandwidth trades with gain.

  46. Q46 medium

    Input bias current of op-amp is

    1. A AC ripple on output only
    2. B slew rate in V/μs
    3. C closed-loop gain in dB only
    4. D average DC current required by the input terminals
    💡 Explanation:

    Bias current flows into BJT bases or FET leakage paths.

  47. Q47 Past Paper · PPSC/FPSC/NTS easy

    Op-amp comparator output saturates to

    1. A always mid-rail without saturation
    2. B analog value proportional to difference in linear mode always
    3. C near positive or negative supply depending on input difference
    4. D zero without supply
    💡 Explanation:

    Without negative feedback op-amp acts as high-gain comparator.

  48. Q48 medium

    Differentiator op-amp circuit uses

    1. A only resistors in both paths
    2. B inductor in feedback without capacitor
    3. C capacitor at the input and resistor in feedback
    4. D Zener diode for clipping only
    💡 Explanation:

    Capacitor passes high-frequency components for differentiation.

  49. Q49 medium

    Integrator op-amp circuit uses

    1. A inductor in input only without capacitor
    2. B capacitor in the feedback path
    3. C resistor-only feedback for integration
    4. D diode bridge in feedback
    💡 Explanation:

    Capacitor integrates input current producing output ∝ ∫vin dt.

  50. Q50 Past Paper · PPSC/FPSC/NTS easy

    Unity-gain buffer (voltage follower) uses

    1. A positive feedback only
    2. B 100% negative feedback from output to inverting input
    3. C no feedback connection
    4. D open-loop operation only
    💡 Explanation:

    Non-inverting input driven; output fed back for V+ ≈ V−.

  51. Q51 medium

    Common-mode rejection ratio (CMRR) measures

    1. A differential gain only without common signal
    2. B output short-circuit current only
    3. C supply voltage ripple only
    4. D ability to reject equal signals applied to both inputs
    💡 Explanation:

    High CMRR suppresses noise appearing on both inputs.

  52. Q52 medium

    Freewheeling diode across an inductive load prevents

    1. A large voltage spikes when switching current off
    2. B forward voltage drop from existing
    3. C oscillator startup without feedback
    4. D op-amp input offset drift
    💡 Explanation:

    Diode provides path for inductive current decay.

  53. Q53 medium

    Slew rate of an op-amp limits

    1. A maximum rate of change of output voltage
    2. B DC gain only
    3. C input bias current only
    4. D common-mode rejection at DC only
    💡 Explanation:

    Internal current limits cap dVout/dt especially for large steps.

  54. Q54 Past Paper · PPSC/FPSC/NTS medium

    Bypass capacitor across emitter resistor in CE stage

    1. A increases AC gain by shorting emitter resistance at signal frequency
    2. B reduces AC gain to zero always
    3. C blocks AC to the base
    4. D replaces collector load
    💡 Explanation:

    AC ground at emitter removes degeneration for signal.

  55. Q55 Past Paper · PPSC/FPSC/NTS medium

    Transformer coupling in amplifiers provides

    1. A infinite bandwidth without leakage inductance
    2. B elimination of all AC coupling
    3. C DC isolation and impedance matching between stages
    4. D direct connection of base to collector
    💡 Explanation:

    Transformer passes AC while blocking DC; can match impedances.

  56. Q56 hard

    Total harmonic distortion (THD) measures

    1. A only DC offset magnitude
    2. B only noise floor without harmonics
    3. C harmonic content relative to fundamental in output
    4. D slew rate limit only
    💡 Explanation:

    THD quantifies nonlinear distortion products.

  57. Q57 medium

    Differential amplifier rejects

    1. A differential signals between inputs
    2. B common-mode signals applied equally to both inputs
    3. C signals on inverting input only without any gain
    4. D supply voltage variations as common-mode always without CMRR limit
    💡 Explanation:

    Matched pair cancels equal inputs; amplifies difference.