Digital Electronics and Logic Design MCQs 2026

The Boolean expression for output of AND gate is

1. A Y = A · B ✓
2. B Y = A + B ✓
3. C Y = A ⊕ B ✓
4. D Y = A′ ✓

NAND gate is functionally equivalent to

1. A inverted OR only without AND ✓
2. B direct AND without inversion ✓
3. C exclusive OR of inputs ✓
4. D inverted AND of its inputs ✓

OR gate output is HIGH when

1. A all inputs are LOW only ✓
2. B any input is HIGH ✓
3. C inputs are equal always ✓
4. D only when inputs differ ✓

NOR gate as a universal gate can implement

1. A only AND functions without NOT ✓
2. B only buffers without inversion ✓
3. C only XOR without other gates ✓
4. D any Boolean function given enough gates ✓

XOR gate output is 1 when

1. A inputs are different ✓
2. B inputs are equal ✓
3. C all inputs are 0 only ✓
4. D both inputs are 1 only ✓

XNOR gate is also called

1. A inverter only ✓
2. B equivalence gate ✓
3. C buffer only ✓
4. D demultiplexer ✓

De Morgan theorem states (A · B)′ equals

1. A A′ + B′ ✓
2. B A′ · B′ ✓
3. C A + B ✓
4. D A ⊕ B ✓

Positive logic defines HIGH as

1. A logic 1 and LOW as logic 0 ✓
2. B logic 0 as HIGH always ✓
3. C analog voltage without digital levels ✓
4. D floating input as definite 1 ✓

Fan-out of a logic gate specifies

1. A maximum number of similar gate inputs it can drive reliably ✓
2. B propagation delay only ✓
3. C supply voltage tolerance only ✓
4. D number of product terms in SOP ✓

Tri-state buffer third state is

1. A always logic 1 ✓
2. B high-impedance output disconnected from logic levels ✓
3. C always logic 0 ✓
4. D short circuit to ground ✓

Propagation delay of a logic gate is

1. A time between input transition and corresponding output transition ✓
2. B DC noise margin only ✓
3. C power dissipation in watts only ✓
4. D number of pins on package ✓

Noise margin indicates

1. A maximum clock frequency only ✓
2. B chip area in mm² only ✓
3. C only DC supply current ✓
4. D allowable noise on input before logic level is misinterpreted ✓

CMOS logic dissipates significant power primarily during

1. A steady state with inputs fixed at valid levels ✓
2. B only when output is high-Z ✓
3. C only at DC with no capacitive load ✓
4. D switching transitions when both PMOS and NMOS briefly conduct ✓

TTL logic HIGH level is typically

1. A 0 V always for HIGH ✓
2. B 12 V without regulation ✓
3. C floating undefined as HIGH without pull-up ✓
4. D around 2.4 V minimum at output for 5 V family ✓

Buffer gate is used to

1. A invert all inputs always ✓
2. B store one bit of memory ✓
3. C isolate loads and restore signal levels without inversion ✓
4. D divide clock frequency by two without flip-flop ✓

Karnaugh map is used for

1. A measuring propagation delay in oscilloscope ✓
2. B calculating Fourier coefficients only ✓
3. C determining ADC resolution only ✓
4. D simplifying Boolean expressions graphically ✓

Adjacent cells in a K-map differ by

1. A two variables always ✓
2. B one variable only (Gray code adjacency) ✓
3. C all variables simultaneously ✓
4. D no systematic rule ✓

A group of 2 adjacent 1s in K-map eliminates

1. A two variables always ✓
2. B no variables ever ✓
3. C one variable from the product term ✓
4. D all variables in the expression ✓

A group of 4 adjacent 1s in a K-map eliminates

1. A one variable only ✓
2. B three variables always ✓
3. C two variables from the product term ✓
4. D no simplification ✓

A group of 8 adjacent 1s on a 4-variable K-map eliminates

1. A three variables ✓
2. B one variable only ✓
3. C all four variables always without remainder ✓
4. D no variables ✓

Don′t-care conditions in K-map are marked as

1. A always 0 without choice ✓
2. B always 1 without choice ✓
3. C X and may be assigned 0 or 1 to maximize groups ✓
4. D ignored without affecting simplification ever ✓

Essential prime implicant is

1. A a prime implicant that covers at least one minterm not covered by any other prime implicant ✓
2. B any group of two cells only ✓
3. C always the largest group without uniqueness ✓
4. D output of OR gate without minimization ✓

Wrap-around adjacency on K-map means

1. A only interior cells can group ✓
2. B edge cells are considered adjacent across map boundaries ✓
3. C diagonal cells always adjacent ✓
4. D cells two steps apart are adjacent ✓

For POS minimization using K-map, groupings are made on

1. A zeros (or maxterms) to obtain sum terms ✓
2. B only 1s without zeros ever ✓
3. C don′t-cares only without zeros ✓
4. D output column of truth table only ✓

Number of cells in K-map for n variables is

1. A n × 2 only ✓
2. B 2^n ✓
3. C n^2 without exponent ✓
4. D 2n only ✓

Redundant group in K-map is one that

1. A is the smallest possible group always ✓
2. B covers only don′t-cares without 1s ✓
3. C does not cover any minterm not already covered by essential groups ✓
4. D cannot be formed on the map ✓

SOP form obtained from K-map is a sum of

1. A only single literals without products ✓
2. B POS maxterms only ✓
3. C NAND operations without OR ✓
4. D product terms (AND terms ORed together) ✓

Five-variable K-map is often implemented as

1. A single row of five cells only ✓
2. B circular map without Gray code ✓
3. C truth table without grouping ✓
4. D two four-variable maps with shifting variable ✓

Overlapping groups in K-map are allowed because

1. A each minterm can appear in only one group always ✓
2. B overlap invalidates simplification ✓
3. C a minterm may participate in multiple groups to form larger coverings ✓
4. D only diagonal overlap is permitted ✓

K-map method is limited compared to Quine-McCluskey for

1. A being less accurate always ✓
2. B inability to handle don′t-cares ever ✓
3. C requiring software always ✓
4. D manual convenience on few variables rather than algorithmic scalability ✓

SR latch built with NOR gates has invalid state when

1. A both inputs are 0 ✓
2. B only S is 0 ✓
3. C only R is 0 with S pulsed ✓
4. D S and R are both 1 simultaneously (active-high inputs) ✓

D flip-flop eliminates

1. A need for clock entirely ✓
2. B all propagation delay ✓
3. C indeterminate condition of SR latch by using single data input ✓
4. D reset pin unconditionally ✓

Positive-edge-triggered flip-flop changes state on

1. A falling edge only always ✓
2. B rising edge of clock ✓
3. C any DC level without transition ✓
4. D both edges simultaneously ✓

JK flip-flop toggles when

1. A J=0 and K=0 always ✓
2. B J and K are both 1 at active clock edge ✓
3. C only asynchronous reset is asserted ✓
4. D clock is held LOW indefinitely ✓

T flip-flop toggles output when

1. A T is 0 at clock edge ✓
2. B reset is deasserted only ✓
3. C T input is 1 at active clock edge ✓
4. D preset alone without clock ✓

Setup time of flip-flop is

1. A minimum time data must be stable before active clock edge ✓
2. B time after clock edge for output change ✓
3. C hold time after edge only without setup ✓
4. D clock period only ✓

Hold time of flip-flop is

1. A time before clock edge only ✓
2. B propagation delay from clock to Q only ✓
3. C minimum time data must remain stable after active clock edge ✓
4. D frequency of oscillator only ✓

Asynchronous preset and clear on flip-flops

1. A override clocked operation immediately when asserted ✓
2. B only work on clock edge like D input ✓
3. C disable all outputs to high-Z always ✓
4. D replace the need for power supply ✓

Master-slave flip-flop reduces

1. A need for setup time entirely ✓
2. B clock frequency to DC only ✓
3. C race conditions by separating capture and output update ✓
4. D power supply decoupling ✓

Metastability occurs when

1. A inputs are stable with large setup margin ✓
2. B power supply is perfectly regulated ✓
3. C only in combinational logic without storage ✓
4. D setup or hold time is violated and output dwells between valid logic levels ✓

Flip-flop propagation delay tpd is

1. A setup plus hold only without output delay ✓
2. B time from clock edge to valid output change at Q ✓
3. C clock period definition only ✓
4. D rise time of power supply only ✓

Register is constructed from

1. A only combinational gates without memory ✓
2. B multiple flip-flops storing parallel bits on common clock ✓
3. C single diode rectifier ✓
4. D op-amp integrator only ✓

Level-sensitive latch differs from edge-triggered FF in that it

1. A is transparent while enable is active ✓
2. B changes only on clock edge always ✓
3. C cannot store any state ✓
4. D requires JK inputs only ✓

Scan flip-flop design aids

1. A only analog amplification ✓
2. B only power factor correction ✓
3. C testing by serially shifting test vectors through the chain ✓
4. D only rectifier ripple reduction ✓

Clock skew between flip-flops can cause

1. A guaranteed faster operation always ✓
2. B elimination of metastability without limit ✓
3. C infinite fan-out capability ✓
4. D timing violations if effective setup/hold margins are reduced ✓

Asynchronous (ripple) counter has

1. A all FFs clocked by common edge simultaneously ✓
2. B flip-flops clocked by previous stage output ✓
3. C no flip-flops only combinational logic ✓
4. D only shift register without counting ✓

Synchronous counter has all flip-flops clocked by

1. A previous stage Q output only ✓
2. B common clock signal ✓
3. C asynchronous preset only without clock ✓
4. D random noise transitions ✓

Modulo-N counter repeats count sequence every

1. A 2^N states always without exception ✓
2. B N squared states ✓
3. C N states ✓
4. D one clock period only ✓

Decade counter (BCD) counts

1. A 0 through 15 in binary always ✓
2. B only even numbers ✓
3. C analog voltage levels without digits ✓
4. D 0 through 9 then returns to 0 ✓

Up-down counter can

1. A only count up without down mode ✓
2. B increment or decrement count on clock depending on control ✓
3. C only operate asynchronously without clock ✓
4. D store analog samples without digital states ✓

Ring counter is implemented with

1. A one hot circulating bit among flip-flops ✓
2. B binary weighted sum only without circulation ✓
3. C Johnson sequence inverted feedback only ✓
4. D K-map groups only ✓

Johnson counter (twisted ring) has sequence length of

1. A n states only ✓
2. B 2^n states always like binary ✓
3. C 2n for n flip-flops ✓
4. D one state only ✓

Counter modulus reduction uses

1. A only increasing clock frequency without feedback ✓
2. B feedback logic to skip states and achieve desired modulo ✓
3. C removing all flip-flops ✓
4. D analog RC timing without digital logic ✓

Glitch problem in asynchronous ripple counter occurs because

1. A stages change at slightly different times producing brief false counts ✓
2. B all bits change simultaneously always ✓
3. C clock is perfectly synchronous by definition ✓
4. D outputs are analog without discrete levels ✓

Presettable counter can be loaded with

1. A only zero without load capability ✓
2. B analog voltage on op-amp input only ✓
3. C only serial shift without parallel load ✓
4. D parallel data to start from a specific initial value ✓

Terminal count output of counter indicates

1. A always midpoint count only ✓
2. B maximum count reached in the sequence ✓
3. C random logic level without definition ✓
4. D analog ramp completion only ✓

Frequency division by 2 per stage in binary counter means

1. A each successive FF toggles at half the previous stage frequency ✓
2. B all stages share identical frequency ✓
3. C frequency doubles each stage ✓
4. D no relation to clock frequency ✓

Synchronous counter typically has

1. A higher cumulative delay than ripple always ✓
2. B no clock input requirement ✓
3. C only one flip-flop regardless of modulus ✓
4. D lower propagation delay uncertainty than ripple counter of same width ✓

Cascade counters achieve

1. A only single-digit BCD without linkage ✓
2. B elimination of clock signal ✓
3. C higher modulus by connecting carry/borrow between stages ✓
4. D purely analog integration without FFs ✓

Digital clock application uses counters for

1. A only DAC conversion without timing ✓
2. B only rectifier filtering ✓
3. C frequency division and time display multiplexing ✓
4. D only motor slip measurement ✓